1. Technical Field
The present invention generally relates to the field of integrated circuit design verification and more particularly to a system and method for managing integrated circuit design verification utilizing modular design verification engines and a verification framework that employ a common interface to facilitate the exchange of verification information and design flows.
2. Description of the Related Art
As the complexity of microprocessors and other sophisticated integrated circuits has increased over the years, the resources devoted to integrated circuit design verification has accounted for an increasingly large percentage of the total resources required to develop and manufacture an integrated circuit. Indeed, the verification of advanced integrated circuits, such as microprocessors with multiprocessing capability, is now estimated to consume more time, labor, and other resources than the actual design of the device.
Traditionally, functional verification has been accomplished by generating a large number of test programs or test cases and running these test programs on a simulator that attempts to model the operation of the device. Designers and verification engineers frequently develop these test cases manually with the help of various random and specific test generators. As the number of transistors, functions, registers, and other facilities in the integrated circuit have increased, conventional verification methods have responded by simply increasing the number of tests that are simulated. Unfortunately, generating a seemingly infinite number of tests is an inefficient and unreliable method of verifying the functionality of all components in the integrated circuit.
In the early days of microprocessor development, inefficiencies in functional verification were tolerated because the size of the test space (measured, for example, by the number of states the microprocessor may assume) was sufficiently small. In addition, early microprocessors typically had fewer functional units than modern microprocessors, and the interactions between the components and functions were well understood and controlled. The increasing number of functional units in microprocessors is significant from a verification perspective because interaction between functional units can no longer be ignored or only loosely verified by conventional verification methodologies.
Because of the many possible applications and uses of modern integrated circuits, integrated circuit designers cannot predict and test every possible real-world configuration in which the integrated circuit may be employed. The test space of a microprocessor is approximately equal to 2n where n represents the number of latches (state storage devices) within the microprocessor. From this approximation, it will be appreciated that the test space of microprocessors increases exponentially as the number of latches is increased.
The conventional approach to functional verification, in which increased complexity in a device is verified by simply increasing the number of tests that are simulated, is rapidly becoming infeasible. In addition, because the input to a simulator in a conventional verification process is simply a large number of deterministic tests or randomly generated tests, the output of the simulation must be painstakingly evaluated to determine whether a particular simulation was successful in testing the intended functionality of the device.
It would be desirable to implement a test verification system that addresses the problems associated with design verification of complex integrated circuits, like microprocessors. It would be further desirable if the implemented system employed a set of modular and relatively compact verification engines that could be invoked in a determinable sequence. It would be further desirable if the system included a verification framework capable of communicating with a user application program to enable the user to create customized sequences comprised of the modular engines and to apply the customized sequence to a defined verification problem.